September 09, 2008 Meeting
TOPIC: "The Past, Present, and Potential Future of Integrated Circuits"
DATE: Tuesday,
September 9th,
2008
Lunch/Chapter business: 11:30 AM - 11:45
P.M.
Program: 11:45 - 12:45 P.M.
LOCATION: Holiday Inn
Select,
Richardson
1655 N. Central Expressway (US
75),
(Southbound frontage road, south of
Campbell)
Richardson, TX 75080
SPEAKER:
Dr. ROBERT R. DOERING,
Senior Fellow, Texas Instruments
Inc.
DOOR PRIZES
Abstract:
This year is the 50th anniversary of Jack Kilby’s 1958 invention of the integrated circuit (IC), for which he won the 2000 Nobel Prize in Physics. Since that invention in a laboratory at Texas Instruments, IC components have been continuously miniaturized, which has resulted in exponential improvement trends in their performance, energy efficiency, and cost per function. These improvements have created a semiconductor industry that has grown to over $250B in annual sales. The process of reducing integrated-circuit component size and associated parameters in a coordinated fashion is traditionally called “feature-size scaling.” Kilby’s original circuit had active (transistor) and passive (resistor, capacitor) components with dimensions of a few millimeters. Today, the minimum feature sizes on integrated circuits are less than 30 nanometers for patterned line widths and down to about one nanometer for film thicknesses. Thus, we have achieved about five orders of magnitude in linear-dimension scaling over the past fifty years, which has resulted in about ten orders of magnitude increase in the density of IC components, a representation of “Moore’s Law.” As IC features are approaching atomic dimensions, increasing emphasis is now being given to the parallel effort of further diversifying the types of components in integrated circuits. This is called “functional scaling” or “More than Moore.” Of course, the enablers for both types of scaling have been developed at many laboratories around the world. The consensus of industry experts is that continuing R&D breakthroughs should allow the traditional feature scaling trend of CMOS technology to continue for approximately another decade, beyond which a radically new information processing paradigm would be needed. Research toward this goal is now underway in universities under the guidance and support of a new industry-government partnership in the U.S.
Biography:
Dr. Doering is a Senior Fellow and Research Strategy Manager at Texas Instruments. He is also a member of TI’s Technical Advisory Board. His previous positions at TI include: Manager of Future-Factory Strategy, Director of Scaled-Technology Integration, and Director of the Microelectronics Manufacturing Science and Technology (MMST) Program. The MMST Program was a 5-year R&D effort, funded by DARPA, the U.S. Air Force, and Texas Instruments, which developed a wide range of new technologies for advanced semiconductor manufacturing. The major highlight of the program was the demonstration, in 1993, of sub-3-day cycle time for manufacturing 350-nm CMOS integrated circuits. This was principally enabled by the development of 100% single-wafer processing.
He received a B.S. degree in physics from the Massachusetts Institute of Technology in 1968 and a Ph.D. in physics from Michigan State University in 1974. He joined TI in 1980, after several years on the faculty of the Physics Department at the University of Virginia. His physics research was on nuclear reactions and was highlighted by the discovery of the Giant Spin-Isospin Resonance in heavy nuclei in 1973 and by pioneering experiments in medium-energy heavy-ion reactions in the late 70’s. His early work at Texas Instruments was on SRAM, DRAM, and NMOS/CMOS device physics and process-flow design. Management responsibilities during his first 10 years at TI included advanced lithography and plasma etch as well as CMOS and DRAM technology development.
Dr. Doering is an IEEE Fellow and Chair of the Semiconductor Manufacturing Technical Committee of the IEEE Electron Devices Society. In addition, he represents Texas Instruments on the Corporate Associates Advisory Committee of the American Institute of Physics. Dr. Doering is also a cofounder of the International Technology Roadmap for Semiconductors and one of the two U.S. representatives to the International Roadmap Committee, which governs the ITRS. He has authored/presented over 150 publications and invited papers/talks and has 20 U.S. patents.
For additional
information, please contact Sue Hui at (214)567-5017, shui@ti.com
or
visit our website: http://www.dallasces.org/